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Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?
(kbin.social)
Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?
Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.
This is VHDL code:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Kitchen_Timer is
port (
clk : in std_logic; -- Clock input
reset : in std_logic; -- Reset input
start : in std_logic; -- Start button input
stop : in std_logic; -- Stop button input
alarm : out std_logic -- Alarm output
);
end entity Kitchen_Timer;
-- Declare the architecture for the kitchen timer
architecture Behavioral of Kitchen_Timer is
signal count : integer range 0 to 3600 := 0; -- Counter for timer
signal alarming : std_logic := '0'; -- Signal to indicate alarming interval
signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval
signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval
begin
-- Process to control the kitchen timer and alarming interval
process (clk, reset)
begin
if (reset = '1') then
count <= 0;
alarming <= '0';
alarm_en <= '0';
alarm_cnt <= 0;
elsif (rising_edge(clk)) then
if (stop = '1') then
count <= 0;
alarming <= '0';
alarm_en <= '0';
alarm_cnt <= 0;
elsif (start = '1' and count < 3600) then
count <= count + 1;
if (count = 3600) then
count <= 0;
alarming <= '0';
alarm_en <= '0';
alarm_cnt <= 0;
elsif (count > 0) then
alarm_en <= '1';
end if;
end if;
if (alarm_en = '1') then
if (alarm_cnt < 600) then
alarm_cnt <= alarm_cnt + 1;
else
alarm_cnt <= 0;
alarming <= '1';
end if;
end if;
end if;
end process;
-- Assign the alarm output
alarm <= alarming;
end architecture Behavioral; ```
This is Testbench:
```library ieee;
use ieee.std_logic_1164.all;
entity tb_Kitchen_Timer is
end tb_Kitchen_Timer;
architecture tb of tb_Kitchen_Timer is
component Kitchen_Timer
port (clk : in std_logic;
reset : in std_logic;
start : in std_logic;
stop : in std_logic;
alarm : out std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal start : std_logic;
signal stop : std_logic;
signal alarm : std_logic;
constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : Kitchen_Timer
port map (clk => clk,
reset => reset,
start => start,
stop => stop,
alarm => alarm);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clk is really your main clock signal
clk <= TbClock;
stimuli : process
begin
-- EDIT Adapt initialization as needed
start <= '0';
stop <= '0';
-- Reset generation
-- EDIT: Check that reset is really your reset signal
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 100 ns;
-- EDIT Add stimuli here
wait for 100 * TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;
-- Configuration block below is required by some simulators. Usually no need to edit.
configuration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is
for tb
end for;
end cfg_tb_Kitchen_Timer;```
#science
